Presentation
Multiple Row Buffer DRAM
DescriptionDRAM chips contain multiple banks to handle several memory requests in parallel. When two memory requests try to access different rows of the same bank, it results in row buffer conflicts. Our objective in this work is to reduce row buffer conflicts by introducing multiple row buffers in each bank. We propose multiple row buffer DRAM, which employs a primary global row buffer along with multiple secondary SRAM row buffers in the DRAM chip. These SRBs act as a cache, exploiting the spatial and temporal locality of memory requests to enhance performance. Our evaluation shows that MRB-DRAM achieves an average improvement in Instructions per Cycle (IPC) of 27% for singlecore systems and a weighted speedup increase of 24% for multicore systems in DDR4 memory configurations with a modest area overhead of approximately 2%.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby