Presentation
Leveraging Artificial Neural Networks for Accurate and Efficient Glitch Propagation Modeling
DescriptionWith continuous technology scaling, accurate and efficient glitch modeling plays a critical role in designing high-performance, low-power, and reliable ICs. In this work, we introduce a new gate-level approach for glitch propagation modeling, utilizing efficient Artificial Neural Networks (ANNs) to accurately estimate the glitch shape characteristics, propagation delay, and power consumption. Moreover, we propose an iterative workflow that seamlessly integrates our models into standard cell libraries, while exploiting the available accuracy and size trade-off. Experimental results on gates implemented in 7 nm FinFET technology demonstrate that our ANNs exhibit a strong correlation with SPICE (R2 over 0.99). Thus, our approach could enable accurate full-chip glitch analysis and effectively guide glitch reduction techniques.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby