Presentation
Enabling Systolic Computing on Elastic Coarse-Grained Reconfigurable Array for HPC and AI
DescriptionSystolic Array is a highly efficient architecture for executing regular and parallel computations, yet its simplicity reduces programmability. In contrast, elastic Coarse-Grained Reconfigurable Array (CGRA) trades simplicity with a more flexible interconnect and execution mode, to run arbitrary dataflow computations. However, efficiently executing highly regular systolic-style computations in CGRA is challenging due to mapping algorithm limitations, data reuse constraints, and mismatching execution controls between systolic and elastic paradigms. This paper explores the tradeoffs of executing systolic-style matrix-matrix multiplication on the elastic CGRA synthesized with the state-of-the-art 3-nm FinFET node in terms of computational throughput and power, performance, and area (PPA).
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby