Presentation
TransRoute: A Novel Hierarchical Transistor-Level Routing Framework Beyond Standard-Cell Methodology
SessionAll You Can Route Buffet
DescriptionIn advanced technology nodes, benefits from scaling have become limited in power, performance, and area, necessitating improvements through design-technology co-optimization (DTCO). However, standard-cell methodology, widely used in VLSI design, restricts the potential of DTCO due to its logic-level abstraction, hindering physical-level optimization. To address this, a transistor-level design approach is needed to break the abstraction of standard cells. While large-scale transistor placement has been explored, efficient routing at the transistor level remains a challenge. This paper introduces a novel transistor-level routing framework with a CP-SAT formulation for lower-layer routing, significantly reducing wirelength and design area compared to traditional standard-cell-based designs.
Event Type
Research Manuscript
TimeTuesday, June 242:45pm - 3:00pm PDT
Location3004, Level 3
EDA7: Physical Design and Verification