Presentation
SynAlign: Annotating HDLs with Synthesis Results
DescriptionIn current chip design processes, multiple tools are often used to obtain a gate-level netlist, resulting in the loss of source code correlation. This paper proposes SynAlign, a tool that addresses the challenges of manual netlist-to-source code tracing by automating the alignment process. SynAlign simplifies the iterative design process, reduces overhead, and maintains correlation across multiple tools, ultimately enhancing the efficiency and effectiveness of chip design workflows. SynAlign can tolerate up to
61% design net changes without impacting alignment accuracy.
61% design net changes without impacting alignment accuracy.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby