Presentation
GEM: GPU-Accelerated Emulator-Inspired RTL Simulation*
DescriptionIn this paper, we present the first GPU-accelerated RTL simulator, addressing critical challenges in high-speed circuit verification. Traditional CPU-based RTL simulators struggle with scalability, and while FPGA-based emulators offer acceleration, they are costly and less accessible. Previous GPU-based attempts have failed to achieve speed-up on RTL simulation due to the irregular nature of circuit graphs, which conflicts with the SIMT (Single Instruction, Multiple Thread) paradigm of GPUs. Inspired by the design of emulators, our approach introduces a novel virtual Very Long Instruction Word (VLIW) architecture, designed for efficient CUDA execution, that maps circuit logic to the GPU in a process analogous to FPGA physical design. This architecture mitigates issues of irregular memory access and thread divergence, unlocking GPU potential for emulation. Our solution achieves remarkable speed-up over the best CPU simulators, democratizing high-speed RTL emulation with accessible hardware and establishing a new frontier for GPU-accelerated circuit verification.
Event Type
Research Manuscript
TimeWednesday, June 254:30pm - 4:45pm PDT
Location3003, Level 3
EDA
EDA2: Design Verification and Validation