Presentation
Deep co-design of a 7.461 TOPS/W/mm^(2) CGRA for Edge-based Perception applications
DescriptionThis paper presents an energy-efficient coarse-grained reconfigurable array (CGRA) architecture tailored for perception applications at the edge, developed using a deep co-design methodology. With a focus on application, compiler, and hardware architecture co-optimization, the proposed CGRA architecture achieves significant energy efficiency per unit area, reaching 7.461TOPS/W/mm^(2) when implemented in a 22nm FD-SOI technology. Our methodology includes customizations at all levels of the CGRA subsystem, facilitating optimized data flow and multi-level parallelism for perception applications. Through strategic design adjustments, the CGRA reduces the computational energy consumption of kernels as low as 9.386nJ, making it ideal for edge-based perception tasks in energy-constrained environments. This work underscores the potential of deep co-design to push the boundaries of energy-efficient computing at the edge, enabling high-performance perception applications in compact, resource-limited systems.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby