Presentation
Design and Technology Co-optimization Utilizing Flip-FET (FFET) Standard Cells
DescriptionWith the continued scaling of VLSI technology beyond 3nm, a consistent demand for layout reduction in standard cells has been made. CFET (Complementary-FET) has been accepted as a promising device technology, stacking N-FET on P-FET (or vice versa) to achieve this goal while providing metal interconnects on both the front and backsides of the wafer through BEOL (back-end-of-line) processing. However, the layout synthesis of CFET based standard cells and its use in physical design implementation are not fully compatible with the effective exploitation of backside interconnects. This is because of a considerable overhead on the allocation of special vias in FEOL (front-end-of-line) referred to as tap-cells, which are essential for the net routes using backside wire. To overcome this drawback of using CFET cells, a new technology called FFET (Flip-FET) has been proposed, which flips the lower FET in CFET to enable direct pin accessibility on both sides of BEOL with no tap cells. In this context, we propose an FFET cell based DTCO methodology to fully utilize backside wires with minimal tap
Event Type
Research Manuscript
TimeWednesday, June 2510:45am - 11:00am PDT
Location3003, Level 3
EDA
EDA8: Design for Manufacturing and Reliability