Presentation
High-Performance Computing Architecture Exploration with Stage-Enhanced Bayesian Optimization
DescriptionThe emergence of new applications in High-Performance Computing is driving the need for more efficient computing machines. As supercomputer architectures become increasingly complex, the combinatorial explosion of design space and time-consuming simulations lead to a challenging design space exploration problem. This work introduces an automated search framework to ease a power-performance-area efficient Arm Neoverse V1 processor design. Based on multi-objective Bayesian optimization, we propose a new exploration algorithm named SEBO by enhancing the three main stages of the optimization. The experimental results show that SEBO can not only compete with the top state-of-the-art baseline algorithms, but also outperform them in terms of the quality and diversity of the returned Pareto-optimal designs.
Event Type
Research Manuscript
TimeTuesday, June 244:30pm - 4:45pm PDT
Location3004, Level 3
EDA
EDA1: Design Methodologies for System-on-Chip and 3D/2.5D System-in Package