Presentation
Opti-SpiSSL: A Highly Reconfigurable Hardware Generation Framework for Spiking Self-Supervised Learning on Heterogeneous SoC
DescriptionOpti-SpiSSL is a reconfigurable hardware framework that optimizes Spiking Self-Supervised Learning (SSL) on heterogeneous System-on-Chip (SoC), addressing challenges with asynchronous, event-driven processing. Leveraging spiking SSL-based optimizations such as neuron density, memory flow, operator fuse with automated code generation and adaptive acceleration, Opti-SpiSSL efficiently balances performance, power, and area through design space exploration (DSE) across FPGA and ASIC. It achieves 28.7% FPS improvement, 37.5% gate reduction, 57.75% area reduction, and 38% resource utilization enhancement, with 0.41s reconfiguration time. Compared to state-of-the-art, Opti-SpiSSL improves 31.9% FPS and 28.8% energy consumption with low resources, offering a scalable, power-efficient solution for next-generation architectures.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby
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