Presentation
Process-Variation-Aware Design Optimization for Wavelength-Routed Optical Networks-on-Chip
DescriptionWavelength-routed optical networks-on-chip (WRONoC) offer low latency and collision-free communication, meeting growing multi-core communication demands. Microring resonators (MRRs), the key components in WRONoC, are susceptible to process variation, causing transmission spectrum shifts, reduced signal power, and increased crosstalk. However, current WRONoC designs have overlooked the impacts of process variation. To counter process variation, we propose a methodology to optimize the MRR radii and signal wavelengths. Specifically, we quantify expected signal power under process variation and propose optimization methods to maximize the expected signal power. Results show up to 7.51 dB improvement in worst-case signal power over designs neglecting process variation.
Event Type
Research Manuscript
TimeTuesday, June 242:30pm - 2:45pm PDT
Location3006, Level 3
EDA
EDA9: Design for Test and Silicon Lifecycle Management