Presentation
HiSpTRSV: Exploring Tile-Level Parallelism for SpTRSV Acceleration on FPGAs
DescriptionSparse Triangular Solve (SpTRSV) is a critical level-2 kernel in sparse Basic Linear Algebra Subprograms (BLAS). While Field-Programmable Gate Array (FPGA) accelerators for SpTRSV focus on optimizing individual tiles, they overlook inter-tile parallelism. Designing an inter-tile parallelism accelerator poses challenges, including constructing fine-grained dependency graph, handling communication overhead, and balancing workloads. HiSpTRSV addresses these challenges through dependency graph parsing, tile-based highly parallel algorithm, filtering mechanisms, and bidirectional matching with modular indexing. Experimental show HiSpTRSV outperforms the state-of-the-art SpTRSV accelerator in terms of a 34.3% performance improvement. HiSpTRSV achieves a 3.58× speedup and 9.59× higher energy efficiency compared to GPUs.
Event Type
Research Manuscript
TimeTuesday, June 244:00pm - 4:15pm PDT
Location3002, Level 3