Presentation
Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner
DescriptionFloorplanning is the initial stage of physical design. However, most existing algorithms focus solely on optimizing half-perimeter wire length (HPWL). This focus often neglects pin assignments for signal transmission and fails to accommodate multiple constraints such as pre-placed modules (PPM). Consequently, this leads to suboptimal power, performance, and area (PPA) metrics, and misaligns with real-world design requirements. To address these challenges, we introduce Piano, a multi-constraint, pin assignment-aware floorplanner that serves as an incremental optimizer for any floorplanning algorithm. Piano constructs a graph based on pin-to-pin connections, enabling effective pin assignments and the calculation of feedthrough paths for long-distance connections. Additionally, it offers a method for whitespace removal and incorporates three operators to enhance pin assignments, while adhering to complex design constraints. Experimental results demonstrate that Piano significantly outperforms recent state-of-the-art approaches in floorplanning, achieving an average reduction of 8% in HPWL and a 23% improvement in unplaced pins.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby
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