Presentation
A Novel Covert Timing Channel for Cloud FPGAs
DescriptionThis paper presents a novel covert timing channel (CTC) that enables a malicious entity to exfiltrate data from a benign cloud FPGA user without requiring dedicated outgoing messages from the cloud FPGA, minimizing the detection risk by both the victim and the cloud service provider. The proposed CTC exploits the handshake signals of the Advanced eXtensible Interface (AXI) protocol and inter-packet delay of the Internet to establish the CTC from a cloud Field-Programmable Gate Array (FPGA) to an off-cloud computer. This paper analyzes the bit-error rate (BER) of the AXI-based CTC under varying conditions and demonstrates its effectiveness in truly enabling remote power analysis attacks on cloud services, such as Amazon Web Services Elastic Compute Cloud (AWS EC2). The proposed CTC achieves a BER as low as 0.01988%.
Event Type
Research Manuscript
TimeTuesday, June 2411:15am - 11:30am PDT
Location3008, Level 3
Security
SEC4: Embedded and Cross-Layer Security