Presentation
An Input-Aware Sparse Tensor Compiler Empowered by Vectorized Acceleration
DescriptionSparsity is widely prevalent in real-world applications, yet existing compiler optimizations and code generation techniques for sparse computations remain underdeveloped. Sparse matrix-matrix multiplication (SpMM) is a representative operator in sparse computations, whose performance is often limited by the design of sparse formats and the extent of hardware architecture optimization. Most existing solutions achieve high-performance SpMM through two approaches: (1) meticulously designed kernels and specialized sparse formats, which require extensive manual effort, or (2) tensor compilers that support code generation, though these typically offer limited support for sparse patterns, making it challenging to adapt to complex sparsity patterns in practical applications. This paper presents SpMMTC, an input-aware sparse tensor compiler. Given a sparse matrix as input, SpMMTC analyzes its non-zero distribution and generates a vectorized kernel optimized for SpMM on the specific matrix. We evaluated SpMMTC on various workloads. It achieves speedups of 1.21x to 2.97x over state-of-the-art methods such as TACO, TVM, and ASpT on different multi-core processors. It also provides an speedup of up to 1.52x for sparse MobileNetV1 inference on the edge device.
Event Type
Research Manuscript
TimeTuesday, June 243:45pm - 4:00pm PDT
Location3008, Level 3
SYS3: Embedded Software