Presentation
SIMAX: Accelerating RTL Simulation for Large-Scale Design
DescriptionRegister Transfer Level (RTL) simulation is a crucial tool in hardware design, widely used in design space exploration, verification, debugging, and preliminary performance evaluation. Among various RTL simulation approaches, software simulation is the most commonly used due to its flexibility, low cost, and ease of debugging. However, the slow speed of simulation has become the bottleneck in verification, due to the extensive overhead required to simulate complex designs.
In this work, we explore the core of RTL simulation and divide it into four stages. For each stage, we propose several techniques to improve the performance. Finally, we implement these techniques in a novel RTL simulator SIMAX. SIMAX succeeds to simulate XiangShan, the state-of-the-art open-source RISC-V processor. Besides, compared to Verilator, SIMAX can achieve speedup of 7.34x for booting Linux in XiangShan, and 19.94x for running CoreMark in RocketChip.
In this work, we explore the core of RTL simulation and divide it into four stages. For each stage, we propose several techniques to improve the performance. Finally, we implement these techniques in a novel RTL simulator SIMAX. SIMAX succeeds to simulate XiangShan, the state-of-the-art open-source RISC-V processor. Besides, compared to Verilator, SIMAX can achieve speedup of 7.34x for booting Linux in XiangShan, and 19.94x for running CoreMark in RocketChip.
Event Type
Research Manuscript
TimeWednesday, June 254:00pm - 4:15pm PDT
Location3003, Level 3
EDA
EDA2: Design Verification and Validation