Presentation
ParLS: A Logic Synthesis Framework based on Circuit Partitioning and Reinforcement Learning
DescriptionLogic synthesis is an important step in digital circuit design, where optimization operators are applied iteratively to improve the quality of results (QoR).
While recent work has made progress in optimizing sequences of operators, these methods typically apply optimization operators directly to the entire circuit, which may lead to suboptimal results due to the heterogeneous nature of different circuit regions.
To address this problem, we propose ParLS, a novel framework that integrates circuit partitioning and reinforcement learning (RL) for finer-grained and efficient optimization.
Specifically, we convert and-inverter graphs (AIGs) into hypergraphs for partitioning, and then use RL to select the most suitable operator for each subgraph based on its characteristics.
Moreover, parallel optimization between subgraphs is utilized to achieve overall acceleration.
Experimental results show that our partition-based optimization framework achieves superior performance across various benchmarks compared to existing optimization methods.
While recent work has made progress in optimizing sequences of operators, these methods typically apply optimization operators directly to the entire circuit, which may lead to suboptimal results due to the heterogeneous nature of different circuit regions.
To address this problem, we propose ParLS, a novel framework that integrates circuit partitioning and reinforcement learning (RL) for finer-grained and efficient optimization.
Specifically, we convert and-inverter graphs (AIGs) into hypergraphs for partitioning, and then use RL to select the most suitable operator for each subgraph based on its characteristics.
Moreover, parallel optimization between subgraphs is utilized to achieve overall acceleration.
Experimental results show that our partition-based optimization framework achieves superior performance across various benchmarks compared to existing optimization methods.
Event Type
Networking
Work-in-Progress Poster
TimeMonday, June 236:00pm - 7:00pm PDT
LocationLevel 2 Lobby