Presentation
GraphDTA: Fast Dynamic Timing Analysis for Circuits with Graph Representation Learning
DescriptionThe conservative nature of static timing analysis (STA) in delay estimation consistently results in overdesign, leading to suboptimal power efficiency and increased area overhead, particularly in compute-intensive AI applications. To address these limitations, this paper introduces GraphDTA, a learning-based dynamic timing analysis (DTA) framework tailored for functional units in AI accelerators. GraphDTA combines graph-based representation learning and downstream model to predict workload-induced dynamic arrival time with high accuracy. We evaluate our approach on 10 benchmarks, including multiplier units (MULs), multiply-accumulate units (MACs) and matrix multiplier units (MMUs), across 45nm and 7nm technologies. Our framework surpasses existing machine learning methods on both technologies and provides roughly 50X speedup compared to the gate-level simulation.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby