Presentation
Guard Ring- and Diffusion-Sharing Embedded FinFET Array Placement
DescriptionWe need proper guard rings to protect devices, especially in advanced nodes. Since they will significantly increase the overall layout area, this work introduces a novel analog circuit placement methodology to enable guard ring sharing with a transistor array layout style. First we construct a hierarchical module clustering tree based on layout constraints, and then creating a guard ring aware transistor placement. Next our stochastic method applies diffusion sharing (by continuous OD) and transition dummies insertion based on Euler path traversal to minimize the total area, while satisfying symmetry, proximity, and matching constraints. Experimental result shows that after applying diffusion sharing and transi- tion dummies insertion, the area can be reduced by 63.9%. Compared to a baseline method without guard ring aware placement, the proposed approach reduces up to 49.8% of the total area on several designs with a commercial 16nm process. Layouts with reduced area show almost no impact on the overall performance.
Event Type
Networking
Work-in-Progress Poster
TimeMonday, June 236:00pm - 7:00pm PDT
LocationLevel 2 Lobby