Presentation
ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
DescriptionIn electronic design automation, logic optimization operators play a crucial role in minimizing the gate count of logic circuits. However, their computation demands are high. Operators such as refactor conventionally form iterative cuts for each node, striving for a more compact representation - a task which often fails 98% on average. Prior research has sought to mitigate computational cost through parallelization. In contrast, our approach leverages a classifier to prune unsuccessful cuts preemptively, thus eliminating unnecessary resynthesis operations. Experiments on the refactor operator using the EPFL benchmark suite and 10 large industrial designs demonstrate that this technique can speedup logic optimization by 3.9× on average compared with the state-of-the-art ABC implementation.
Event Type
Research Manuscript
TimeTuesday, June 244:30pm - 4:45pm PDT
Location3006, Level 3