Presentation
Megabits Down to Kilobits: Memory-Efficient Time-Aware Shaping for TSN
DescriptionTime-Sensitive Networking (TSN) provides bounded latency and low jitter for cyber-physical systems, such as industrial control. As a key component of TSN, the Time-Aware Shaper (TAS) applies gate control rules to control the transmission time of frames in critical flows. TAS stores the gate control rules for each frame in the gate control table. However, in typical industrial setups, the memory usage of the table could reach over tens of megabits and even exceed the total memory capacity of TSN switches.
To address this issue, we propose a memory-efficient TAS design named METAS. It transitions from a per-frame to a \textit{per-flow} approach. METAS stores one \textit{persistent rule} for a flow and dynamically generates a \textit{temporary rule} for a frame only when the frame arrives. We prototyped METAS on an FPGA, and experimental results show that METAS reduces memory usage from 14.34 Mbits to 288 Kbits when supporting 1,024 flows, using just 1.56\% of the FPGA's logic resources while maintaining microsecond-level latency and nanosecond-level jitter for critical flows.
To address this issue, we propose a memory-efficient TAS design named METAS. It transitions from a per-frame to a \textit{per-flow} approach. METAS stores one \textit{persistent rule} for a flow and dynamically generates a \textit{temporary rule} for a frame only when the frame arrives. We prototyped METAS on an FPGA, and experimental results show that METAS reduces memory usage from 14.34 Mbits to 288 Kbits when supporting 1,024 flows, using just 1.56\% of the FPGA's logic resources while maintaining microsecond-level latency and nanosecond-level jitter for critical flows.
Event Type
Research Manuscript
TimeWednesday, June 254:00pm - 4:15pm PDT
Location3008, Level 3
Systems
SYS6: Time-Critical and Fault-Tolerant System Design