Presentation
Directed on-the-fly Validation of Hierarchical Cache Coherence Protocols
DescriptionRecent advancements in memory technologies and programming models have heightened the demand for sophisticated memory hierarchies. A critical aspect of these hierarchies is the implementation of cache coherence protocols, which play a pivotal role in maintaining data integrity across multi-core memory systems. Despite the availability of various validation techniques—such as random testing, constrained random testing, and formal verification—these approaches often prove to be either unreliable or resource-intensive, requiring significant time and memory to guarantee protocol correctness. Existing directed testing frameworks, while promising, frequently encounter challenges such as state space explosion and the potential omission of critical states if not meticulously applied. To address these limitations, we propose an enhanced on-the-fly directed validation method specifically designed for cache coherence protocols. This approach achieves comprehensive state and transition coverage with approximately 50% fewer test cases, all without increasing memory overheads, offering a more efficient and effective solution for validating coherence protocols in complex memory hierarchies.
Event Type
Networking
Work-in-Progress Poster
TimeMonday, June 236:00pm - 7:00pm PDT
LocationLevel 2 Lobby