Presentation
Expanding Logical Space Freely: A Memory-efficient Mapping Table Design for Compressional SSDs
DescriptionCompressional SSDs can be a mixed blessing. While they offer users increased logical space beyond the physical capacity, they also complicate the internal design of the Flash Translation Layer (FTL) by requiring a larger Logical-to-Physical (L2P) address mapping.
In this paper, we propose a novel N-to-1 L2P mapping table design that consolidates multiple logical entries into a single entry. This approach eliminates the duplication of physical page numbers when a physical page contains several compressed logical pages, significantly reducing the memory footprint of compressional SSDs.To accommodate the dynamic compression ratios of real-world workloads, we introduce promotion and demotion schemes that enable mapping table entries to migrate between pages with different compression ratios. Additionally, to address the issue of partial invalidation—where some compressed logical pages within a physical page are invalid due to the N-to-1 mapping—we present a compression-aware garbage collection (GC) algorithm aimed at minimizing the number of copy operations for partially invalid physical pages.
We have implemented our design in MQsim, a widely used SSD simulator, and have conducted a series of experiments to evaluate the effectiveness of the proposed techniques. The results demonstrate that our approach significantly reduces the mapping table size in compressional SSDs, leading to an improved mapping table cache hit ratio and a reduced I/O latency compared to traditional compressional SSDs.
In this paper, we propose a novel N-to-1 L2P mapping table design that consolidates multiple logical entries into a single entry. This approach eliminates the duplication of physical page numbers when a physical page contains several compressed logical pages, significantly reducing the memory footprint of compressional SSDs.To accommodate the dynamic compression ratios of real-world workloads, we introduce promotion and demotion schemes that enable mapping table entries to migrate between pages with different compression ratios. Additionally, to address the issue of partial invalidation—where some compressed logical pages within a physical page are invalid due to the N-to-1 mapping—we present a compression-aware garbage collection (GC) algorithm aimed at minimizing the number of copy operations for partially invalid physical pages.
We have implemented our design in MQsim, a widely used SSD simulator, and have conducted a series of experiments to evaluate the effectiveness of the proposed techniques. The results demonstrate that our approach significantly reduces the mapping table size in compressional SSDs, leading to an improved mapping table cache hit ratio and a reduced I/O latency compared to traditional compressional SSDs.
Event Type
Research Manuscript
TimeMonday, June 232:30pm - 2:45pm PDT
Location3008, Level 3