Presentation
A Graph-Based Approach for Optimizing Pin Access in Nanosheet FET Standard Cell Library Synthesis
DescriptionThis paper addresses the challenges associated with standard cell synthesis for Nanosheet FET technology, particularly the constraints on M2 layer usage and the need to consider M0 and M1 layers in block-level routing. We propose a flexible synthesis flow that can dynamically switch between single-row and multi-row cell structures. To improve pin accessibility, we introduce a method for dynamic pin allocation on M0 and M1 layers, along with techniques to limit M0 pin length and mitigate vertical pin access conflicts. Experimental results demonstrate that our method outperforms both hand-crafted and existing automated cell libraries in terms of area (3.2%), DRV count (77.1% to 97.6%), and wirelength (16.5%) in block-level physical synthesis.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby