Presentation
GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs
DescriptionCoarse-grained reconfigurable architecture (CGRA) has emerged as a promising solution for accelerating computationally intensive applications, particularly in the field of artificial intelligence. One of the primary challenges for CGRA compilers is generating effective mapping results for complex applications within a limited timeframe. This paper presents an enhanced pre-scheduling method that integrates Integer Linear Programming (ILP) and Graph Neural Networks (GNN), along with a corresponding two-stage mapping approach. This combination significantly reduces the search space and accelerates the solution process for mapping problems. Experimental results demonstrate performance improvements ranging from 29.4% to 406.7%, along with compilation time reductions of up to 1106.8x compared to existing compilation techniques, as well as excellent scalability.
Event Type
Research Manuscript
TimeTuesday, June 244:45pm - 5:00pm PDT
Location3002, Level 3
Design
DES1: SoC, Heterogeneous, and Reconfigurable Architectures