Presentation
Incompatible: Test Quality and Fortuitous Detection
DescriptionRecent publications have reported that the root-cause of SDEs (silent date errors) include defects that escape manufacturing testing. An escaped defect is due to its behavior deviating from what is predicted by the models and metrics utilized for test generation. In order to reduce escape, the first step must involve understanding how often and in what manner does defect behavior deviate from the models/metrics used for ATPG (automatic test pattern generation). In this work, we describe and demonstrate a methodology for precisely deriving defect behavior from ATE (automatic test equipment) data collected from a failing logic circuit. The gap measured between models/metrics and actual defect behavior for a 14nm industrial test chip is so substantial that we conclude that test quality can only be maintained and improved if fortuitous detection is reduced. In other words, understanding and minimizing the deviations between predicted behavior and actual defect behavior are crucial for enhancing test quality in the context of SDEs.
Event Type
Research Special Session
TimeTuesday, June 241:30pm - 2:00pm PDT
Location3010, Level 3
EDA