Presentation
Enhancing Test Quality by Targeting Timing Marginalities Due to Process Variations
DescriptionIncreasing random process variations that impact device parameters in low-nanometer nodes are introducing unpredictable circuit delays and timing marginalities. These can cause failures under adverse operating conditions in some manufactured instances of a design. Such faulty circuits often escape manufacturing tests because current scan timing tests are generated under the assumption of a single localized delay fault in the circuit; accumulation of distributed delays in a circuit path from variations in multiple gates is not targeted because path delay tests have not proven practical. While the increasing use of at-speed functional tests does detect some variability failures, the coverage of functional tests is known to be limited. This talk examines extreme slow paths from process variations, extracting some unique characteristics that can be exploited by structural test methods to more effectively screen out many such failures. The aim is to improve test quality and DPPM levels from postproduction testing.
Event Type
Research Special Session
TimeTuesday, June 242:00pm - 2:30pm PDT
Location3010, Level 3
EDA