Presentation
Device-Aware Test: A Means to Attack Unmodeled Defects
DescriptionThis talk discusses a new test approach called Device-Aware Test (DAT) and applies it to industrial STT-MRAMs designs. DAT is a new test approach that goes beyond Cell-Aware Test; it does not assume that a defect in a device can be modeled electrically as a linear resistor (as the state-of-the art approach suggests), but it rather incorporates the impact of the physical defect into the technology parameters of the device and thereafter in its electrical parameters. Once the defective electrical model is defined, a systematic fault analysis is performed to derive appropriate fault models and subsequently test solutions. DAT is demonstrated on real STT-MRAM chips, which suffer from unique defects such as pinhole, synthetic anti-ferrimagnet flip, back-hoping, etc. The measurements show that DAT sensitizes realistic faults as well as new unique defects and faults that can never be caught with the traditional approaches.
Event Type
Research Special Session
TimeTuesday, June 242:30pm - 3:00pm PDT
Location3010, Level 3
EDA