Presentation
Energy-Efficient On-Device AI Acceleration and More Enabled By 3D Integration
DescriptionSilicon design for Augmented Reality (AR) presents a unique challenge of enabling high performance applications in a small form factor. AR products require machine learning algorithms, neural networks, image signal processing applications, and more to run on energy-efficient platforms that are heavily constrained in area footprint. The third dimension, however, usually has ample space. To enable these applications to be energy-efficient, memory accesses to off-accelerator and/or off-chip can be prohibitively expensive. This paper presents recent results in utilizing a combination of face-to-face stacking technology with hybrid bonding and circuit design techniques to enable more immersive applications such as group calling with Pixel Codec Avatars to be run on AR systems-on-chip (SoCs) at 2× better energy-efficiency compared to equivalent 2D accelerators at iso-footprint. Moreover, we show that this combination of 3D integration technology and circuit design techniques can be extended beyond just digital systems-on-chip to other AR chips such as display drivers, enabling higher bit-depth displays at lower power with smaller area footprint.
Event Type
Research Special Session
TimeTuesday, June 2410:30am - 11:00am PDT
Location3010, Level 3
AI
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