Presentation
Advanced Package Design & System Co-Optimization for Heterogeneous Integration
DescriptionHeterogeneous integration has moved from a novel concept just a few years ago to a mainstay in the computer industry. Advanced packaging is a key part of any chiplet architecture strategy. The concept of heterogeneous integration is inviting, with the ability to mix and match chiplets from different design sources as well as foundry nodes. This enables scaled architectures to address high-computing needs for memory and enhanced compute with accelerators. The approach also promises cost-optimization and faster time to market. All these benefits cannot be realized, however, without careful consideration of the advanced packaging design and the optimization of the package design within the system construct. This includes co-optimization all the way from silicon to the system, and packaging is in the middle of this and critical. This talk covers the key role that advanced packaging plays in enabling optimized chiplet architectures and the important design considerations. Key trade-off studies that are needed early in the concept phase will be discussed, highlighting areas like power, thermal, I/O, mechanical and cost. The talk will touch upon co-design, early architecture studies, standards, and the need for interoperable tools/flows/methods as well as innovations in design and optimization approaches to ensure optimum performance while keeping cost in mind.
Event Type
Research Special Session
TimeTuesday, June 243:30pm - 4:00pm PDT
Location3010, Level 3