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Presenter

Ankur Bal
STMicroelectronics
Presentations
Engineering Poster
Automated Topology based Pin Access Checker for Correct by Construction Standard Cells Design
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Front-End Design
Engineering Poster
Networking
Advanced APL Modeling Method for Complex I/O Buffer Designs for accurate SoC IR Drop Analysis
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
High Figure of Merit Polyphase Decimation Core IP
11:30am - 11:45am PDT Wednesday, June 25 2010, Level 2
IP
Engineering Presentation
Mitigation of Functional Power Dissipation in Parasitic Scan Shift Test Buffers
4:06pm - 4:24pm PDT Tuesday, June 24 2012, Level 2
Back-End Design
Chiplet
Engineering Poster
Networking
Reducing Top Level Verification Cycle of High Frequency PLLs with Enhanced Fast-SPICE Technology
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
A Robust and Efficient Verification Suite for AMS IP HDL Models for Streamlined SoC Integration
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Front-End Design
Engineering Poster
Automated – BUS Routing Solution for Efficient DRC clean TestChip Design
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Front-End Design
Engineering Presentation
Statistical analysis using AI-ML enabled SPICE solution to get tail samples for high linearity delta sigma converters
11:30am - 11:45am PDT Monday, June 23 2010, Level 2
AI
IP