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Presenter

Haoxing Ren
Nvidia
Presentations
Research Manuscript
INSTA: An Ultra-Fast, Differentiable, Statistical Static Timing Analysis Engine for Industrial Physical Design Applications*
10:30am - 10:45am PDT Monday, June 23 3004, Level 3
EDA
EDA3: Timing Analysis and Optimization
Workshop
First International Workshop on Synergizing AI and Circuit-System Simulation
1:30pm - 5:00pm PDT Sunday, June 22 3003, Level 3
AI
Sunday Program
Research Manuscript
ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation
2:45pm - 3:00pm PDT Monday, June 23 3000, Level 3
AI
AI1: AI/ML Algorithms
Research Manuscript
GEM: GPU-Accelerated Emulator-Inspired RTL Simulation*
4:30pm - 4:45pm PDT Wednesday, June 25 3003, Level 3
EDA
EDA2: Design Verification and Validation
Research Manuscript
Reinforcement Learning-Driven Window Selection for Enhanced Window-Based Rip-up and Reroute in Chip Detailed Routing
2:15pm - 2:30pm PDT Tuesday, June 24 3004, Level 3
EDA
EDA7: Physical Design and Verification
Research Manuscript
DCO-3D: Differentiable Congestion Optimization in 3D ICs
1:45pm - 2:00pm PDT Wednesday, June 25 3006, Level 3
EDA
EDA7: Physical Design and Verification
Chair of Sessions
Engineering Presentation
AI and Chiplet/Multi-die: Verification Scalability and AI driven Automation
3:30pm - 5:00pm PDT Tuesday, June 24 2010, Level 2
AI
Front-End Design
Chiplet