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Mingxuan Yuan
Huawei
Presentations
Research Manuscript
Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving
5:00pm - 5:15pm PDT Wednesday, June 25 3004, Level 3
EDA
EDA2: Design Verification and Validation
Research Manuscript
ReMaP: Macro Placement by Recursively Prototyping and Periphery-Guided Relocating
10:45am - 11:00am PDT Wednesday, June 25 3006, Level 3
EDA
EDA7: Physical Design and Verification
Research Manuscript
LLMShare: Optimizing LLM Inference Serving with Hardware Architecture Exploration
1:45pm - 2:00pm PDT Tuesday, June 24 3002, Level 3
AI
AI4: AI/ML System and Platform Design
Networking
Work-in-Progress Poster
Compact Thermal Model-Based Analytical 3D Chip Placement with GPU Acceleration
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
DES5: Emerging Device and Interconnect Technologies
Research Manuscript
smaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
11:30am - 11:45am PDT Wednesday, June 25 3004, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis
Networking
Work-in-Progress Poster
Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
DES5: Emerging Device and Interconnect Technologies
Research Manuscript
EDGE: DBMS-Empowered Boolean Decomposition for GIG Synthesis
4:00pm - 4:15pm PDT Tuesday, June 24 3006, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis
Networking
Work-in-Progress Poster
PPA-driven Placement via Adaptive Cluster Constraints Optimization
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
DES5: Emerging Device and Interconnect Technologies
Networking
Work-in-Progress Poster
FuncFormer: Circuit Representation Learning via the Flow of Functional Propagation
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
DES5: Emerging Device and Interconnect Technologies
Research Manuscript
ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
4:30pm - 4:45pm PDT Tuesday, June 24 3006, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis