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Presenter

Mohamed Atoua
Siemens
Presentations
Engineering Poster
AI-Based Trimming and Optimization for Voltage Regulators: Proven Accuracy with Wafer Data
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Accelerating Bandgap Reference High-Sigma Verification with Additive AI Technology
11:00am - 11:15am PDT Monday, June 23 2010, Level 2
AI
IP
Engineering Poster
Networking
Advanced Yield Prediction for SRAM Bitcells with Rare Defect Modeling Leveraging AI-Powered Methodology
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Accelerating SRAM Design Cycles With Additive AI Technology
10:30am - 10:45am PDT Monday, June 23 2010, Level 2
AI
IP
Engineering Poster
Networking
Accelerating Chip Design with AI-Powered Additive Learning for Deep Sub-Micron Technologies
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall