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Presenter

Zhiyao Xie
Hong Kong University of Science and Technology (HKUST)
Presentations
Research Manuscript
ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
4:45pm - 5:00pm PDT Monday, June 23 3006, Level 3
EDA
EDA4: Power Analysis and Optimization
Tutorial
Introduction to Foundation AI Model and Its EDA Applications
1:30pm - 5:00pm PDT Sunday, June 22 3004, Level 3
Sunday Program
Research Manuscript
SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits
2:30pm - 2:45pm PDT Tuesday, June 24 3001, Level 3
AI
AI2: AI/ML Application and Infrastructure
Networking
Work-in-Progress Poster
DAPO: Design Structure Aware Pass Ordering in High-Level Synthesis with Graph Contrastive and Reinforcement Learning
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
DES5: Emerging Device and Interconnect Technologies
Research Manuscript
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
2:00pm - 2:15pm PDT Tuesday, June 24 3001, Level 3
AI
AI2: AI/ML Application and Infrastructure
Research Manuscript
AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling
5:15pm - 5:30pm PDT Wednesday, June 25 3006, Level 3
Systems
SYS4: Embedded System Design Tools and Methodologies
Research Manuscript
ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
4:30pm - 4:45pm PDT Tuesday, June 24 3006, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis
Chair of Sessions
Research Manuscript
Breakthroughs in Timing Prediction, Analysis, and Optimization
10:30am - 12:00pm PDT Monday, June 23 3004, Level 3
EDA
EDA3: Timing Analysis and Optimization