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Presenter

Xiaoxin Xu
Institute of Microelectronics, Chinese Academy of Sciences
Presentations
Research Manuscript
An Energy-Efficient High-Utilization Hardware Architecture for Attention Mechanism in Transformer using Balanced Systolic Array and Multi-Row Interleaved Operation Ordering
2:30pm - 2:45pm PDT Monday, June 23 3001, Level 3
AI
AI3: AI/ML Architecture Design
Research Manuscript
A PulseWidth-IN-PulseWidth-Out Universal Nonlinear Processing Element for Time-Domain In-Memory Computing Systems
11:00am - 11:15am PDT Monday, June 23 3002, Level 3
Design
DES2A: In-memory and Near-memory Computing Circuits
Research Manuscript
Re4PUF: A Reliable, Reconfigurable ReRAM-based PUF Resilient to DNN and Side Channel Attacks
2:15pm - 2:30pm PDT Wednesday, June 25 3008, Level 3
Security
SEC2: Hardware Security: Primitives & Architecture, Design & Test