Presenter

I am a Design Verification Engineer with 9 years of experience in the semiconductor industry. Since joining Intel in 2015, I have played a key role in delivering high-quality SoC IP designs and have specialized in IP/SoC verification, focusing on power management flows, PCIe Gen6 LTSSM, and RAS flows for Intel Xeon processors. I hold a master's degree in VLSI Design and Embedded Systems, which complements my technical background.