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Presenter

Avinash Chaudhary
Texas Instruments
Presentations
Engineering Presentation
AACT: Automated Analog Coverage Tool for Mixed Signal Verification
10:45am - 11:00am PDT Wednesday, June 25 2008, Level 2
Front-End Design
Engineering Poster
Networking
Revolutionising SOC Verification through System Verilog EEnet-Enhanced Behavioural Model for Precision in Analog IP Characterisation
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall