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Presenter

Jianwang Zhai
Beijing University of Posts and Telecommunications
Presentations
Networking
Work-in-Progress Poster
ParLS: A Logic Synthesis Framework based on Circuit Partitioning and Reinforcement Learning
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
DES5: Emerging Device and Interconnect Technologies
Research Manuscript
HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design
3:30pm - 3:45pm PDT Tuesday, June 24 3002, Level 3
Design
DES1: SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM Acceleration
3:45pm - 4:00pm PDT Tuesday, June 24 3002, Level 3
Design
DES1: SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
Truly Pre-Routing Timing Prediction via Considering Power Delivery Networks
11:15am - 11:30am PDT Monday, June 23 3004, Level 3
EDA
EDA3: Timing Analysis and Optimization
Networking
Work-in-Progress Poster
HLSRanker: Design Space Exploration in High-Level Synthesis Using Preference Bayesian Optimization
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
DES5: Emerging Device and Interconnect Technologies
Research Manuscript
IRGNN: A Graph-based Framework Integrating Numerical Solution and Point Cloud for Static IR Drop Prediction
3:45pm - 4:00pm PDT Monday, June 23 3006, Level 3
EDA
EDA4: Power Analysis and Optimization