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Presenter

Jie Zhou
Southeast University
Presentations
Research Manuscript
Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
4:15pm - 4:30pm PDT Wednesday, June 25 3003, Level 3
EDA
EDA2: Design Verification and Validation
Research Manuscript
Location is Key: Leveraging LLM for Functional Bug Localization in Verilog Design
5:15pm - 5:30pm PDT Tuesday, June 24 3008, Level 3
Systems
SYS3: Embedded Software
Research Manuscript
UVLLM: An Automated Universal RTL Verification Framework using LLMs
4:30pm - 4:45pm PDT Wednesday, June 25 3006, Level 3
Systems
SYS4: Embedded System Design Tools and Methodologies