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Naveen Bishnoi
Intel Corporation
Presentations
Engineering Poster
Networking
A Novel Approach For Logic Equivalence Check After Pipeline Retiming in ECO
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Enhancing Timing Closure in High-Frequency Designs through Precise Latency Control and Timing-Aware Sink Assignment
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall