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Presenter

Hailong Yao
University of Science and Technology of China
Presentations
Research Manuscript
PatLabor: Pareto Optimization of Timing-Driven Routing Trees
1:30pm - 1:45pm PDT Tuesday, June 24 3004, Level 3
EDA
EDA7: Physical Design and Verification
Networking
Work-in-Progress Poster
PECA: Polyhedral-Based Efficient Compiler for AI Applications on CGRAs
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
DES5: Emerging Device and Interconnect Technologies
Research Manuscript
GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs
4:45pm - 5:00pm PDT Tuesday, June 24 3002, Level 3
Design
DES1: SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
Mr.TPL: A New Multi-pin Routing Method for Triple Patterning Lithography
2:30pm - 2:45pm PDT Tuesday, June 24 3004, Level 3
EDA
EDA7: Physical Design and Verification