Close

Presenter

Ehsan Degan
IBM
Presentations
Networking
Work-in-Progress Poster
CIRCUITSYNTH-RL: LLM-Based Circuit Topology Synthesis with RL Refinement
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Networking
Work-in-Progress Poster
DiReC: Enhancing VHDL Code Generation and Summarization with Divide-Retrieve-Conquer Strategy
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Networking
Work-in-Progress Poster
RTLExplain: A Structured Approach to RTL Code Summarization and Question Answering for Medium-to-Large Designs Using LLMs
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Networking
Work-in-Progress Poster
Enhancing LLMs for HDL Code Optimization using Domain Knowledge Injection
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby