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Presenter

Akshita Bansal
Cadence Design Systems, Inc.
Presentations
Engineering Poster
Automated – BUS Routing Solution for Efficient DRC clean TestChip Design
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Automated Topology based Pin Access Checker for Correct by Construction Standard Cells Design
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall