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Presenter

Davide Sanalitro
STMicroelectronics
Presentations
Engineering Presentation
Enhancing verification throughput in random tests regression with a novel machine learning engine
3:30pm - 3:45pm PDT Tuesday, June 24 2010, Level 2
AI
Front-End Design
Chiplet
Engineering Presentation
A novel approach to generate random/constrained Non-Volatile-Memory content in a UVM environment
2:30pm - 2:45pm PDT Monday, June 23 2010, Level 2
AI
IP
Chiplet
Engineering Poster
Networking
Unlocking the power of AI-based verification apps for an innovative and efficient digital verification flow
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Accelerating analog connectivity verification with Jasper: comparing formal methods to mixed simulation
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall