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Presenter

Zhe Lin
Sun Yat-sen University
Presentations
Research Manuscript
HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design
3:30pm - 3:45pm PDT Tuesday, June 24 3002, Level 3
Design
DES1: SoC, Heterogeneous, and Reconfigurable Architectures
Networking
Work-in-Progress Poster
HLSRanker: Design Space Exploration in High-Level Synthesis Using Preference Bayesian Optimization
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
DES5: Emerging Device and Interconnect Technologies
Research Manuscript
VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM Acceleration
3:45pm - 4:00pm PDT Tuesday, June 24 3002, Level 3
Design
DES1: SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs
2:00pm - 2:15pm PDT Wednesday, June 25 3004, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis