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Presenter

Shaowei Cai
Institute of Software, Chinese Academy of Sciences
Presentations
Research Manuscript
Parallel Dynamic Partitioning for Datapath Combinational Equivalence Checking
5:15pm - 5:30pm PDT Wednesday, June 25 3003, Level 3
EDA
EDA2: Design Verification and Validation
Research Manuscript
X-SAT: An Efficient Circuit-Based SAT Solver
3:45pm - 4:00pm PDT Wednesday, June 25 3004, Level 3
EDA
EDA2: Design Verification and Validation
Research Manuscript
PastATPG: A Hybrid ATPG Framework for Better Test Compaction with Partial Assignment SAT
2:15pm - 2:30pm PDT Tuesday, June 24 3006, Level 3
EDA
EDA9: Design for Test and Silicon Lifecycle Management
Research Manuscript
Leveraging Critical Proof Obligations for Efficient IC3 Verification
4:15pm - 4:30pm PDT Wednesday, June 25 3004, Level 3
EDA
EDA2: Design Verification and Validation