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Presenter

Siyuan Xu
Huawei
Presentations
Networking
Work-in-Progress Poster
Compact Thermal Model-Based Analytical 3D Chip Placement with GPU Acceleration
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
DES5: Emerging Device and Interconnect Technologies
Research Manuscript
ReMaP: Macro Placement by Recursively Prototyping and Periphery-Guided Relocating
10:45am - 11:00am PDT Wednesday, June 25 3006, Level 3
EDA
EDA7: Physical Design and Verification
Networking
Work-in-Progress Poster
PPA-driven Placement via Adaptive Cluster Constraints Optimization
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
DES5: Emerging Device and Interconnect Technologies
Networking
Work-in-Progress Poster
Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
DES5: Emerging Device and Interconnect Technologies