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Presenter

Yi-Wei Chen
Intel Corporation
Presentations
Engineering Presentation
PPA Evaluation of BS-PDN Compared to FS-PDN in the Early Stage
4:24pm - 4:42pm PDT Tuesday, June 24 2012, Level 2
Back-End Design
Chiplet
Engineering Presentation
3DIC Thermal-Aware Early Design Optimization
3:48pm - 4:06pm PDT Tuesday, June 24 2012, Level 2
Back-End Design
Chiplet
Engineering Presentation
Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
3:45pm - 4:00pm PDT Monday, June 23 2008, Level 2
AI
Systems and Software
Chiplet