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Yiting Lin
Ansys
Presentations
Engineering Poster
Networking
From Block, Chip to System - A Comprehensive flow for large FPGA Dynamic Power Integrity Sign-off
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Sign-off Challenges and Solutions in Power Integrity and Reliability Analysis of 2.5DIC Silicon Interposer
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall